Enabling the Vitis Kernel Flow - 2021.2 English

Vitis High-Level Synthesis User Guide (UG1399)

Document ID
UG1399
ft:locale
English (United States)
Release Date
2021-12-15
Version
2021.2 English

When you select the Vitis Kernel Flow Target on the Solution Settings dialog box, as discussed in Creating a New Vitis HLS Project, you are configuring Vitis HLS to generate the compiled kernel object (.xo) for the Vitis application acceleration flow. The Vitis Kernel flow is more restrictive than the Vivado IP flow, and the kernels produced by the HLS tool must meet the specific requirements of the platforms and Xilinx runtime (XRT), as described in Kernel Properties in the Vitis Unified Software Platform Documentation .

The flow selection is enabled with the open_solution -flow_target vitis command.

When specifying open_solution -flow_target vitis, or enabling the Vitis Kernel Flow in the IDE, Vitis HLS implements interface ports using the AXI standard as described in Interfaces for Vitis Kernel Flow.

The solution is updated to include two new configuration commands:

config_rtl -register_reset_num=3

and

config_interface -default_slave_interface=s_axilite -m_axi_latency=64 \
-m_axi_alignment_byte_size=64 -m_axi_max_widen_bitwidth=512 -m_axi_offset=slave

The config_rtl command defines characteristics of the RTL code generated by Vitis HLS, specifically defining characteristics of the reset required by the Vitis application acceleration development flow.

The config_interface command sets characteristics of the default interface protocols the tool assigns. If there are no existing Interface pragmas in the code, then the following interface protocols will be applied.

  • AXI4-Lite interfaces (s_axilite) are assigned to scalar arguments, global variables, control signals for arrays, and the return value of the software function.
  • AXI4 Master interfaces (m_axi) are assigned to pointer and array arguments of the C/C++ function.
  • Vitis HLS automatically tries to infer BURST transactions whenever possible to aggregate memory accesses to maximize the throughput bandwidth and/or minimize the latency.
  • Defining a software function argument using an hls::stream data type implies an AXI4-Stream (axis) port.

You can manually assign the interface specification for your function argument, using the INTERFACE pragma or set_directive_interface command. You can use this technique to change the settings of the default interfaces, such as -bundle to group function arguments into AXI interfaces, and -max_read/write_burst_length to manage burst transactions.