Enabling the Vivado IP Flow - 2021.2 English

Vitis High-Level Synthesis User Guide (UG1399)

Document ID
UG1399
ft:locale
English (United States)
Release Date
2021-12-15
Version
2021.2 English

When you select the Vivado IP Flow Target on the Solution Settings dialog box, as discussed in Creating a New Vitis HLS Project, you are configuring Vitis HLS to generate RTL IP files for use in the Vivado Design Suite, for inclusion in the IP catalog, and for use in block designs of the IP integrator tool. HLS synthesis transforms your C or C++ code into register transfer level (RTL) code that you can synthesize and implement into the programmable logic region of a Xilinx device.

The flow selection is enabled with the open_solution -flow_target vivado command.

The Vivado IP flow is more flexible and less structured than the Vitis Kernel flow. Vivado IP can support a wide variety of interface specifications and data transfer protocols, and does not naturally support the Xilinx runtime (XRT) requirements of the Vitis system. The Vivado IP flow provides much greater discretion in your design choices, however, leaves the integration and management of the IP up to you as well.

The Vivado IP flow has default interfaces assigned to function arguments as described in Interfaces for Vivado IP Flow. You can also override the default settings by manually assigning the interface specification for your function argument, using the INTERFACE pragma or set_directive_interface command, to meet the needs of your Vivado design.