Exporting the RTL Design

Vitis High-Level Synthesis User Guide (UG1399)

Document ID
UG1399
ft:locale
English (United States)
Release Date
2021-12-15
Version
2021.2 English

The final step in the Vitis HLS flow is to export the RTL design in a form that can be used by other tools in the Xilinx design flow. Click the Export RTL command in the Flow Navigator to open the Export RTL dialog box shown in the following figure.

Tip: When Vitis HLS reports the results of the high-level synthesis, it only provides an estimate of the results with projected clock frequencies and resource utilization (LUTs, DSPs, BRAMs, etc.). These results are only estimates because Vitis HLS cannot know what optimizations or routing delays will be in the final synthesized or implemented design. Therefore use the Run Implementation command from Flow Navigator to return reports from Vivado synthesis or place and route.
Figure 1. Export RTL Dialog Box
Table 1. RTL Export Selections
Export Format Default Location Comments
Vivado IP (.zip) solution/impl/export.zip

The IP is exported as a ZIP file that can be added to the Vivado IP catalog.

The impl/ip folder also contains the contents of the unzipped IP.

Vitis Kernel (.xo) solution/impl/export.xo

The XO file output can be used for linking by the Vitis compiler in the application acceleration development flow.

You can link the Vitis kernel with other kernels, and the target accelerator card, to build the xclbin file for your accelerated application.

Vivado IP for System Generator solution/impl/ip

This option creates IP for use with the Vivado edition of System Generator for DSP.

Output Location
Lets you specify the path and file name for the exported RTL design.
IP OOC XDC File
Specifies an XDC file to be used for the RTL IP for out-of-context (OOC) synthesis.
IP XDC File
Lets you specify an XDC file for use during Vivado place and route.

IP Configuration

When you select the Vivado IP format on the Export RTL dialog box, you also have the option of configuring specific fields, such as the Vendor, Library, Name, and Version (VLNV) of the IP.

The Configuration information is used to differentiate between multiple instances of the same IP when it is loaded into the Vivado IP catalog. For example, if an implementation is packaged for the IP catalog, and then a new solution is created and packaged as IP, the new solution by default has the same name and configuration information. If the new solution is also added to the IP catalog, the IP catalog will identify it as an updated version of the same IP and the last version added to the IP catalog will be used.

The Configuration options, and their default values are listed below:

Vendor
xilinx.com
Library
hls
Version
1.0
Description
An IP generated by Vitis HLS
Display Name
This field is left blank by default
Taxonomy
This field is left blank by default

After the IP packaging process is complete, the ZIP file archive written to the specified Output Location, or written in the solution/impl folder, can be imported into the Vivado IP catalog and used in any design.

Software Driver Files

For designs that include AXI4-Lite slave interfaces, a set of software driver files is created during the export process. These C driver files can be included in a Vitis embedded software development project, and used to access the AXI4-Lite slave port.

The software driver files are written to directory solution/impl/ip/drivers and are included in the packaged IP export.zip. Refer to AXI4-Lite Interface for details on the C driver files.