The top-level function becomes the top level of the RTL design after synthesis. Sub-functions are synthesized into blocks in the RTL design.
Global variables used by the kernel cannot be accessed from the outside. Any variable that is accessed by both the testbench (or other compiled kernels or host) and the kernel itself should be an explicit argument of the kernel.
After synthesis, each function in the design has its own synthesis report and HDL file (Verilog and VHDL).