By default, AMD Vitis™ HLS groups function arguments with
compatible options into a single
m_axi/s_axilite interface adapter.
Bundling ports into a single interface helps save device resources by eliminating AXI4
logic, which can be necessary when working in congested designs. However, a single
interface bundle can limit the performance of the kernel because all the memory
transfers have to go through a single interface. For example, the
interface has independent READ and WRITE channels, so a single interface
can read and write simultaneously, though only at one location. Using multiple bundles
lets you increase the bandwidth and throughput of the kernel by creating multiple
interfaces to connect to memory banks.
Bundle rules for AXI interfaces are fully described in M_AXI Bundles/S_AXILITE Bundles section in the user guide (UG1399) and should be reviewed before proceeding further.