The arguments of the top-level function in a Vitis HLS design are synthesized into interfaces and
ports that group multiple signals to define the communication protocol between the
HLS design and components external to the design. Vitis HLS defines interfaces automatically, using industry standards
to specify the protocol used. The type of interfaces that Vitis HLS creates depends on the data type and direction of the
parameters of the top-level function, the target flow for the active solution, the
default interface configuration settings as specified by
, and any specified INTERFACE pragmas or directives.
- The Vivado IP flow which is the default flow for the tool
- The Vitis Kernel flow, which is the bottom-up design flow for the Vitis Application Acceleration Development flow
open_solution -flow_target [vitis | vivado]
- The interface defines channels for data to flow into or out of the HLS design. Data can flow from a variety of sources external to the kernel or IP, such as a host application, an external camera or sensor, or from another kernel or IP implemented on the Xilinx device. The default channels for Vitis kernels are AXI adapters as described in Interfaces for Vitis Kernel Flow.
- The interface defines the port protocol that is used to
control the flow of data through the data channel, defining when the data is
valid and can be read or can be written, as defined in Port-Level I/O Protocols. Tip: These port protocols can be customized in the Vivado IP flow, but are set and cannot be changed in the Vitis kernel flow, in most cases.
- The interface also defines the execution control scheme for the HLS design, specifying the operation of the kernel or IP as pipelined or sequential, as defined in Block-Level Control Protocols.
As described in Designing Efficient Kernels the choice and configuration of interfaces is a key to the success of your design. However, Vitis HLS tries to simplify the process by selecting default interfaces for the target flows. For more information on the defaults used refer to Interfaces for Vivado IP Flow or Interfaces for Vitis Kernel Flow as appropriate to your design.
After synthesis completes you can review the mapping of the software arguments of your C/C++ code to hardware ports or interfaces in the SW I/O Information section of the Synthesis Summary report.