M_AXI Bundles - 2021.2 English

Vitis High-Level Synthesis User Guide (UG1399)

Document ID
UG1399
ft:locale
English (United States)
Release Date
2021-12-15
Version
2021.2 English

Vitis HLS groups function arguments with compatible options into a single m_axi interface adapter. Bundling ports into a single interface helps save FPGA resources by eliminating AXI logic, but it can limit the performance of the kernel because all the memory transfers have to go through a single interface. The m_axi interface has independent READ and WRITE channels, so a single interface can read and write simultaneously, though only at one location. Using multiple bundles the bandwidth and throughput of the kernel can be increased by creating multiple interfaces to connect to multiple memory banks.

In the following example all the pointer arguments are grouped into a single m_axi adapter using the interface option bundle=BUS_A, and adds a single s_axilite adapter for the m_axi offsets, the scalar argument size, and the function return.

extern "C" {
void vadd(const unsigned int *in1, // Read-Only Vector 1
          const unsigned int *in2, // Read-Only Vector 2
          unsigned int *out,     // Output Result
          int size                 // Size in integer
          ) {
 
#pragma HLS INTERFACE mode=m_axi bundle=BUS_A port=out
#pragma HLS INTERFACE mode=m_axi bundle=BUS_A port=in1
#pragma HLS INTERFACE mode=m_axi bundle=BUS_A port=in2
#pragma HLS INTERFACE mode=s_axilite port=in1
#pragma HLS INTERFACE mode=s_axilite port=in2
#pragma HLS INTERFACE mode=s_axilite port=out
#pragma HLS INTERFACE mode=s_axilite port=size
#pragma HLS INTERFACE mode=s_axilite port=return
Figure 1. MAXI and S_AXILITE

You can also choose to bundle function arguments into separate interface adapters as shown in the following code. Here the argument in2 is grouped into a separate interface adapter with bundle=BUS_B. This creates a new m_axi interface adapter for port in2.

extern "C" {
void vadd(const unsigned int *in1, // Read-Only Vector 1
          const unsigned int *in2, // Read-Only Vector 2
          unsigned int *out,     // Output Result
          int size                 // Size in integer
          ) {
 
#pragma HLS INTERFACE mode=m_axi bundle=BUS_A port=out
#pragma HLS INTERFACE mode=m_axi bundle=BUS_A port=in1
#pragma HLS INTERFACE mode=m_axi bundle=BUS_B port=in2
#pragma HLS INTERFACE mode=s_axilite port=in1
#pragma HLS INTERFACE mode=s_axilite port=in2
#pragma HLS INTERFACE mode=s_axilite port=out
#pragma HLS INTERFACE mode=s_axilite port=size
#pragma HLS INTERFACE mode=s_axilite port=return
Figure 2. 2 MAXI Bundles

Bundle Rules

The global configuration command config_interface -m_axi_auto_max_ports false will limit the number of interface bundles to the minimum required. It will allow the tool to group compatible ports into a single m_axi interface. The default setting for this command is disabled (false), but you can enable it to maximize bandwidth by creating a separate m_axi adapter for each port.

With m_axi_auto_max_ports disabled, the following are some rules for how the tool handles bundles under different circumstances:

  1. Default Bundle Name: The tool groups all interface ports with no bundle name into a single m_axi interface port using the tool default name bundle=<default>, and names the RTL port m_axi_<default>. The following pragmas:
    #pragma HLS INTERFACE mode=m_axi port=a depth=50 
    #pragma HLS INTERFACE mode=m_axi port=a depth=50
    #pragma HLS INTERFACE mode=m_axi port=a depth=50 
    

    Result in the following messages:

    INFO: [RTGEN 206-500] Setting interface mode on port 'example/gmem' to 'm_axi'.
    INFO: [RTGEN 206-500] Setting interface mode on port 'example/gmem' to 'm_axi'.
    INFO: [RTGEN 206-500] Setting interface mode on port 'example/gmem' to 'm_axi'.
    
  2. User-Specified Bundle Names: The tool groups all interface ports with the same user-specified bundle=<string> into the same m_axi interface port, and names the RTL port the value specified by m_axi_<string>. Ports without bundle assignments are grouped into the default bundle as described above. The following pragmas:
    #pragma HLS INTERFACE mode=m_axi port=a depth=50 bundle=BUS_A
    #pragma HLS INTERFACE mode=m_axi port=b depth=50
    #pragma HLS INTERFACE mode=m_axi port=c depth=50
    

    Result in the following messages:

    INFO: [RTGEN 206-500] Setting interface mode on port 'example/BUS_A' to 'm_axi'.
    INFO: [RTGEN 206-500] Setting interface mode on port 'example/gmem' to 'm_axi'.
    INFO: [RTGEN 206-500] Setting interface mode on port 'example/gmem' to 'm_axi'.
    
    Important: If you bundle incompatible interfaces Vitis HLS issues a message and ignores the bundle assignment.