The AXI Master Adapter converts the customized AXI commands from the HLS scheduler to standard AXI AMBA protocol and sends them to the external memory. The MAXI adapter uses resources such as FIFO to store the requests/Data and ack. Here is the summary of the modules and the resource they consume:
- Write Module: The bus write modules performs the write operations.
FIFO_wreq: This FIFO module stores the future write requests. When the AW channel is available a new write request to global memory will be popped out of this FIFO.
buff_wdata: This FIFO stores the future write data that needs to be sent to the global memory. When the W channel is available and AXI protocol conditions are met, the write data of size= burst_length will be popped out of this FIFO and sent to the global memory.
FIFO_resp: This module is responsible for controlling the number of pipelined outstanding requests sent to the global memory.
- Read Module: These modules perform the read operations. It uses the
FIFO_rreq: This FIFO module stores the future write requests. When the AR channel is free a read request to global memory will be popped out of this FIFO.
buff_rdata: This FIFO stores the read data that are received from the global memory.
The device resource consumption of the M_AXI adapter is a sum of all the
write modules (size of the
buff_wdata, and size of FIFO_ resp) and the sum of all read
modules. In general, the size of the FIFO is calculated as = Width * Depth. When you
refer to a 1KB FIFO storage it can be one of the configurations such as 32*32, 8*64 etc,
which are selected according to the design specification. Similarly, the adapter FIFO
storage can be globally configured for the design using the following options of the
These configuration options control the width and depth of the FIFO as shown below.
- Size of the
rreq module= (width(
config_interface -m_axi_addr64[=true|false])) * Depth(
config_interface -m_axi_latency)). This FIFO will be implemented as a shift register by the Vivado tool.
Size of the
buff_wdatamodule = (width ( port width after HLS synthesis) * Depth (
config_interface -m_axi_max_read/write_burst_length)).Tip: This FIFO by default will be implemented as BRAM, but it can be implemented in LUTRAM or URAM as determined by
- Size of the
FIFO_respmodule = width(2) * depth (