In the Vitis unified IDE the hierarchy of the HLS component is structured as follows: <workspace>/<component>/<component>/hls/. You can select the HLS component in the Vitis Component Explorer and select Open In Terminal from the right-click menu to explore the contents of the component folders.
When synthesis completes, the syn folder is created inside the <component>/hls folder. This folder contains the following elements:
- The verilog and vhdl folders contain the output RTL files.
- The top-level file has the same name as the top-level function for synthesis.
- There is one RTL file created for each sub-function that has not been inlined into a higher level function.
- There could be additional RTL files to implement sub-blocks of the RTL hierarchy, such as block RAM, and pipelined multipliers.
- The report folder contains a report file for the top-level function and one for every sub-function that has not been in-lined into a higher level function by the HLS compiler. The report for the top-level function provides details on the entire design.