Output of C/RTL Co-Simulation - 2021.2 English

Vitis High-Level Synthesis User Guide (UG1399)

Document ID
UG1399
ft:locale
English (United States)
Release Date
2021-12-15
Version
2021.2 English
When C/RTL Cosimulation completes, the sim folder is created inside the solution folder. This folder contains the following elements:
  • The sim/report folder contains the report and log file for each type of RTL simulated.
  • A verification folder named sim/verilog or vhdl is created for each RTL language that is verified.
    • The RTL files used for simulation are stored in the verilog or vhdl folder.
    • The RTL simulation is executed in the verification folder.
    • Any outputs, such as trace files and waveform files, are written to the verilog or vhdl folder.
  • Additional folders sim/autowrap, tv, wrap and wrap_pc are work folders used by Vitis HLS. There are no user files in these folders.
Tip: If the Setup Only option was selected in the C/RTL Co-Simulation dialog box, an executable is created in the verification folder but the simulation is not run. The simulation can be manually run by executing the simulation .exe at the command prompt.