Output of RTL Export - 2021.2 English

Vitis High-Level Synthesis User Guide (UG1399)

Document ID
UG1399
ft:locale
English (United States)
Release Date
2021-12-15
Version
2021.2 English

Vitis HLS writes to the impl folder of the active solution folder when you run the Export RTL command.

The output files and folders include the following:

  • component.xml: The IP component file that defines the interfaces and architecture.
  • export.zip: The zip archive of the IP and its contents. The zip file can be directly added to the Vivado IP catalog.
  • export.xo: The compiled kernel object for use in the Vitis application acceleration development flow.
  • impl/ip: The IP contents unzipped.
  • impl/ip/example: A folder with a Tcl script used to generate the packaged IP, and a shell script to export the IP.
  • impl/report: The report for the synthesized, or placed and routed IP is written to this folder.
  • impl/verilog: Contains the Verilog format RTL output files.
  • impl/vhdl: Contains the VHDL format RTL output files.
    Tip: If the Vivado synthesis or Vivado synthesis, place, and route options are selected, Vivado synthesis and implementation are performed in the Verilog or VHDL folders. In this case the folder includes a project.xpr file that can be opened in the Vivado Design Suite.
Important: Xilinx does not recommend directly using the files in the verilog or vhdl folders for your own RTL synthesis project. Instead, Xilinx recommends using the packaged IP output files. Please carefully read the text that immediately follows this note.

In cases where Vitis HLS uses Xilinx IP in the design, such as with floating point designs, the RTL directory includes a script to create the IP during RTL synthesis. If the files in the verilog or vhdl folders are copied out and used for RTL synthesis, it is your responsibility to correctly use any script files present in those folders. If the package IP is used, this process is performed automatically by the design Xilinx tools. If C/RTL co-simulation has been executed in Vitis HLS, the Vivado project also contains an RTL test bench, and the design can be simulated.