Output of RTL Export - 2023.2 English

Vitis High-Level Synthesis User Guide (UG1399)
Document ID
UG1399
Release Date
2023-12-18
Version
2023.2 English

The HLS compiler writes to the impl folder of the active solution folder when you run the Package command.

The output files and folders include the following:

  • component.xml: The IP component file that defines the interfaces and architecture.
  • <component_name>.zip: The zip archive of the IP and its contents. The zip file can be directly added to the Vivado IP catalog.
  • <component_name>.xo: The compiled kernel object for use in the Vitis application acceleration development flow.
  • impl/ip: The IP contents unzipped.
  • impl/ip/example: A folder with a Tcl script used to generate the packaged IP, and a shell script to export the IP.
  • impl/report: The report for the synthesized, or placed and routed IP is written to this folder.
  • impl/verilog: Contains the Verilog format RTL output files.
  • impl/vhdl: Contains the VHDL format RTL output files.
    Tip: If the Implementation step in Flow Navigator is performed, the output folders also include the project.xpr file that can be opened in the Vivado Design Suite.
Important: You should not use the files in the verilog or vhdl output folders directly for your own use. Instead, use the packaged IP output files (impl/ip) for the resons stated below.

In cases where the HLS compiler uses Vivado IP in the synthesized design, such as with floating point designs, the impl/verilog or impl/vhdl directory includes a script to create the IP during RTL synthesis. If the files in the verilog or vhdl folders are copied out and used for RTL synthesis, it is your responsibility to correctly use any script files present in those folders. If the package IP output files (impl/ip) are used, this process is performed automatically. If C/RTL co-simulation has been executed in the HLS component, the Vivado project also contains an RTL test bench, and the design can be simulated.