Make sure the HLS component is active in the Flow Navigator, or select it from the Component menu to make it the active component in the tool. When the HLS component is the active component, the Flow Navigator enables running C Simulation, C Synthesis, C/RTL Co-simulation, Packaging, and Implementation to build and analyze the HLS component. For C/RTL Co-simulation of the HLS component select Run beneath the C/RTL COSIMULATION heading in the Flow Navigator.
Running Co-simulation on the HLS component requires a test bench, or test bench files, which must be loaded as described in Running C Simulation. Prior to running co-simulation you must also configure the HLS component to support C/RTL co-simulation. Configure the design using the following steps.
not supported for co-simulation. It is recommended that random values be generated once
and saved to a file which the C/C++ test bench can then use during co-simulation.
Configure the Simulator
You can configure the simulator prior to running simulation using the C/RTL Co-Simulation section of the Config Editor, as shown below.
These configuration commands let you specify how the simulation should run. These configuration commands are all documented in Co-Simulation Configuration. Refer to that content for more detailed information. Some of the settings for C/RTL Co-Simulation include the following:
- Specifies the level of trace file output written to the
sim/Verilog or sim/VHDL directory of the current solution
when the simulation executes. Options include:
- Output all port and signal waveform data being saved to the trace file.
- Output waveform trace data for the top-level ports only.
- Output waveform trace data for the complete port hierarchy.
- Do not output trace data.
- Applies a randomized stall for each data transmission.
- Enables waveform visualization of all processes in the RTL simulation. This option is only supported when using Vivado logic simulator. Enabling this will launch the Simulator GUI to let you examine dataflow activity in the waveforms generated by simulation. Refer to the Vivado Design Suite User Guide: Logic Simulation (UG900) for more information on that tool.
- Disables deadlock detection, and opening the Cosim Deadlock Detection in co-simulation.
- Enables capturing profile data for display in the Dataflow Viewer.
- Dynamic Deadlock Prevention
- Prevent deadlocks by enabling automatic FIFO channel size tuning for dataflow profiling during co-simulation.
Run C/RTL Co-Simulation
With the C/RTL Co-simulation setup defined in the config file you
are ready to select Run from the
Flow Navigator to
begin simulation. You can track the progress of simulation in the
Output window. The
transcript for the synthesis run will have the top function name as
<component-name>::co_simulation as shown
vitis-run --mode hls --cosim command as described in
vitis, v++, and vitis-run Commands.
After the simulation is complete you should see the Co_simulation finished successfully message at the end of the transcript. You will also see the Reports folder under the Run command populated as shown in the preceding figure. The reports available after co-simulation include:
- Summary: reports the command line used and the time stamp on the results.
displays general information about the design, displays specific options used
during Co-simulation, and displays performance and resource estimates for the
design hierarchy. If
enable_dataflow_profilingis enabled, performance data will be back annotated to the Dataflow Viewer report as described in Dataflow Viewer.Important: If you want to calculate II, you must ensure there are at least two transactions in the RTL simulation as described in Writing a Test Bench.
- Timeline Trace: As described in Timeline Trace Viewer.
- Wave Viewer: As described in Viewing Simulation Waveforms.
- Function Call Graph: Displays the post Co-simulation call graph as described in Function Call Graph.