The Vitis HLS tool is limited in terms of the estimations it can provide about the RTL design that it generates. It can project resource utilization and timing of the end result, but these are just projections. To get a better view of the RTL design, you can actually run Vivado synthesis and place and route on the generated RTL design, and review actual results of timing and resource utilization. Select the Run Implementation command from the Flow Navigator to open the dialog box as shown below.
The dialog presents the choice of running RTL Synthesis or RTL Synthesis, Place & Route. The dialog box is largely unchanged in either selection, with the exception of the Place & Route Options that appear at the bottom.
- Generate RTL in Verilog or VHDL form.
- Clock Period
- Specify the clock period, which is defined by the active solution by default.
- Generate DCP
- Check box to generate a DCP file for the synthesized or implemented design.
- IP Location
- Specify the location to write the generated IP file.
- IP OOC XDC File
- Specifies an XDC file to be used for the RTL IP for out-of-context (OOC) synthesis.
- IP XDC File
- Lets you specify an XDC file for use during Vivado place and route.
- Report Level
- Defines the report-level generated during synthesis or implementation.
- Max Timing Paths
- Specify the number of timing paths to extract from the Timing Summary report. The worst case paths are returned as defined by the specified value.
- RTL Synthesis Strategy
- Specify the strategy to employ in the synthesis run.
- Synth Design Arguments
- Specify options for the
- Run Physical Optimizations
- Specify the physical optimization to run. Choices include:
- Implementation Strategy
- Specify the strategy to employ in the implementation run.