S_AXI Lite - 2021.2 English

Vitis High-Level Synthesis User Guide (UG1399)

Document ID
UG1399
ft:locale
English (United States)
Release Date
2021-12-15
Version
2021.2 English

User-Defined and Default Bundle Names

Rule 1: User-specified Bundle Name
Important: The Vitis Kernel flow only supports a single s_axilite interface. Creating multiple bundles in this flow, either explicitly or implicitly, will result in an error during synthesis.
This rule explicitly groups all interface ports with the same bundle=<string> into the same AXI4-Lite interface port and names the RTL port the value specified by s_axi_<string>.
void top(char *a, char *b, char *c, char *d) { 
#pragma HLS INTERFACE s_axilite port=a bundle=terry 
#pragma HLS INTERFACE s_axilite port=b bundle=terry 
#pragma HLS INTERFACE s_axilite port=c bundle=stephen 
#pragma HLS INTERFACE s_axilite port=d bundle=jim 
}
INFO: [RTGEN 206-100] Bundling port 'd' to AXI-Lite port jim. 
INFO: [RTGEN 206-100] Bundling port 'c' to AXI-Lite port stephen. 
INFO: [RTGEN 206-100] Bundling port 'a' and 'b' to AXI-Lite port terry. 
INFO: [RTGEN 206-100] Finished creating RTL model for 'example'
Rule 2: Default Bundle Name
This rule explicitly groups all interface ports with no bundle name into the same AXI4-Lite interface port, and uses tool default bundle=<deafult>, and names the RTL port s_axi_<default>.
void top(char *a, char *b, char *c, char *d) { 
#pragma HLS INTERFACE s_axilite port=a 
#pragma HLS INTERFACE s_axilite port=b 
#pragma HLS INTERFACE s_axilite port=c 
#pragma HLS INTERFACE s_axilite port=d 
}
Log fileINFO: [RTGEN 206-100] Bundling port 'a', 'b', 'c' to AXI-Lite port control. 
INFO: [RTGEN 206-100] Finished creating RTL model for 'example'.
Rule 3: Partially Specified Bundle Name
If the bundle names are partially specified, then the tool will create more than one s_axi lite interface port. See the following bundle rules:
  • This rule explicitly groups all interface ports with which the bundle name "control" (default name) is specified into the same AXI4-Lite Interface port.
  • This rule also explicitly groups all the remaining un-specified bundle names to the new default name which does not conflict with any user names.
void top(char *a, char *b, char *c, char *d) { 
#pragma HLS INTERFACE s_axilite port=a 
#pragma HLS INTERFACE s_axilite port=b 
#pragma HLS INTERFACE s_axilite port=c bundle=control 
#pragma HLS INTERFACE s_axilite port=d bundle=control 
}
INFO: [RTGEN 206-100] Bundling port 'c' and 'd' to AXI-Lite port control. 
INFO: [RTGEN 206-100] Bundling port 'a' and 'b' to AXI-Lite port control_r. 
INFO: [RTGEN 206-100] Finished creating RTL model for 'example'.