Simulating IP Cores - 2021.2 English

Vitis High-Level Synthesis User Guide (UG1399)

Document ID
UG1399
ft:locale
English (United States)
Release Date
2021-12-15
Version
2021.2 English

When the design is implemented with floating-point cores, bit-accurate models of the floating-point cores must be made available to the RTL simulator. This is automatically accomplished if the RTL simulation is performed using the Vivado logic simulator. However, for supported third-party HDL simulators, the Xilinx floating-point library must be pre-compiled and added to the simulator libraries.

For example, to compile the Xilinx floating-point library in Verilog for use with the VCS simulator, open the Vivado IDE and enter the following command in the Tcl Console window:

compile_simlib -simulator vcs_mx -family all -language verilog

This creates the floating-point library in the current directory for VCS. See the Vivado Tcl Console window for the directory name. In this example, it is ./rev3_1.

You must refer to this library from within theVitis HLS IDE by specifying the Compiled Library Location field in the Co-simulation dialog box as described in C/RTL Co-Simulation in Vitis HLS, or by running C/RTL co-simulation using the following command:

cosim_design -tool vcs -compiled_library_dir <path_to_library>/rev3_1