Target Flow Overview - 2023.2 English

Vitis High-Level Synthesis User Guide (UG1399)

Document ID
UG1399
Release Date
2023-12-18
Version
2023.2 English

The HLS component can target either the Vivado IP flow, or the Vitis Kernel flow. The HLS component is implemented based on the target flow, default tool configuration, design constraints, and any optimization pragmas or directives you specify. You can use optimization directives to modify and control the implementation of the internal logic and I/O ports, overriding the default behaviors of the tool.

Vivado IP Flow

When you select the Vivado IP Flow on the Settings page of the Create HLS Component wizard, or specify flow_target=vivado in the HLS configuration file, you are configuring the tool to generate RTL files for use in the Vivado Design Suite, for use with other RTL files and Vivado IP, and for use with software applications using software to interact with the hardware.

The Vivado IP can be implemented into the programmable logic (PL) region of an AMD Versal™ adaptive SoC, AMD Zynq™ MPSoC, or AMD FPGA device. The IP is generated with device drivers so the PL can be integrated with embedded software applications to manage and run the hardware functions as described in the Vitis Embedded Software Development Flow Documentation (UG1400).

The Vivado IP flow provides greater flexibility in your design choices over the Vitis kernel flow, however it leaves the integration and management of the IP to you as well. The Vivado IP flow can support a wide variety of interface specifications and data transfer protocols, but has default interfaces assigned to function arguments as described in Interfaces for Vivado IP Flow. You can also override the default settings by manually assigning the interface specification for your function argument, using the INTERFACE pragma or set_directive_interface command, to meet the needs of your Vivado design.

Vitis Kernel Flow

When you select the Vitis Kernel Flow on the Settings page of the Create HLS Component wizard, or specify flow_target=vitis in the HLS configuration file, you are configuring the tool to generate an RTL design suitable for use in the Vitis development environment and for use with the Xilinx Runtime (XRT). The Vitis development flow can be used in embedded system design for heterogeneous compute systems for AMD Versal™ adaptive SoC, AMD Zynq™ MPSoC devices, or for Data Center application acceleration running on Alveo accelerator cards as described in Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393). The Vitis development flow is more restrictive than the Vivado IP flow, as the design requirements for RTL produced by the HLS tool must meet the specific requirements of the platforms and Xilinx Runtime (XRT).

When specifying the Vitis Kernel Flow in the IDE, the tool implements interface ports using the AXI standard as described in Interfaces for Vitis Kernel Flow. If there are no existing INTERFACE pragmas or directives in the code, then the following interface protocols will be applied by default.

  • AXI4-Lite interfaces (s_axilite) are assigned to scalar arguments, control signals for arrays, and the return value of the software function.
  • AXI4 Master interfaces (m_axi) are assigned to pointer and array arguments of the C/C++ function.
  • Vitis HLS automatically tries to infer BURST transactions whenever possible to aggregate memory accesses to maximize the throughput bandwidth and/or minimize the latency.
  • Defining a software function argument using an hls::stream data type implies an AXI4-Stream (axis) port.