Timeline Trace Viewer - 2021.2 English

Vitis High-Level Synthesis User Guide (UG1399)

Document ID
UG1399
ft:locale
English (United States)
Release Date
2021-12-15
Version
2021.2 English

Timeline Trace view is a new viewer introduced to show the run time profile of the functions of your design. It is especially useful to see the behavior of dataflow regions after Co-simulation, as there is no need to launch the Vivado logic simulator to view the timeline.

Timeline Trace viewer displays multiple iterations through the various sub-functions of a dataflow region, shows where the functions are starting and ending, and displays the Co-simulation data in tables below the timeline.

There are basic tools to use while viewing the timeline, such as adding markers and stepping from one marker to the next, and measuring the time between markers.

Figure 1. Timeline Trace Viewer

You can generate the Timeline Trace view from RTL Co-simulation. You should enable Dump Trace All, and Enable Channel Profiling options from the Co-Sumlation dialog box, or from the Solutions Settings dialog box, and the Co-Sim window.