Working with Sources - 2021.2 English

Vitis High-Level Synthesis User Guide (UG1399)

Document ID
UG1399
ft:locale
English (United States)
Release Date
2021-12-15
Version
2021.2 English

The following figure illustrates the Vitis HLS design flow, showing the inputs and output files.

Figure 1. Vitis HLS Design Flow

Vitis HLS inputs include:

  • C functions written in C and C++11/C++14. This is the primary input to Vitis HLS. The function can contain a hierarchy of sub-functions.
  • C functions with RTL blackbox content as described in Adding RTL Blackbox Functions.
  • Design Constraints that specify the clock period, clock uncertainty, and the device target.
  • Directives are optional and direct the synthesis process to implement a specific behavior or optimization.
  • C test bench and any associated files needed to simulate the C function prior to synthesis, and to verify the RTL output using C/RTL Co-simulation.

You can add the C input files, directives, and constraints to a project using the Vitis HLS graphical user interface (GUI), or using Tcl commands from the command prompt, as described in Running Vitis HLS from the Command Line. You can also create a Tcl script, and execute the commands in batch mode.

The following are Vitis HLS outputs:

  • Compiled object files (.xo).

    This output lets you create compiled hardware functions for use in the Vitis application acceleration development flow. Vitis HLS produces this output when called as part of the compilation process from the Vitis tool flow, or when invoked as a stand-alone tool in the bottom up flow.

  • RTL implementation files in hardware description language (HDL) formats.

    This is a primary output from Vitis HLS. This flow lets you use C/C++ code as a source for hardware design in the Vitis tool flow. RTL IP produced by Vitis HLS is available in both Verilog (IEEE 1364-2001), and VHDL (IEEE 1076-2000) standards, and can be synthesized and implemented into Xilinx devices using the Vivado Design Suite.

  • Report files.

    Reports generated as a result of simulation, synthesis, C/RTL co-simulation, and generating output.