Configures various attributes of the output RTL, the type of reset used, and the encoding of the state machines. It also allows you to use specific identification in the RTL.
By default, these options are applied to the top-level design and all RTL blocks within the design. You can optionally specify a specific RTL model.
-deadlock_detection <none | sim | hw>
- Enables simulation or synthesis deadlock detection in top
level RTL of exported IP/XO file. The options are as follows:
- none : Deadlock detection disabled
- sim : Enables deadlock detection only for simulation/emulation (default)
Deadlock detection enabled in synthesized and simulatable RTL IP.
ap_local_blocksignals to the IP to enable local and global deadlock detection.
- Disables the automatic selection of free-running pipelines (FRP) by Vitis HLS.
Note: This option has no effect for FRP manually selected using the PIPELINE pragma or directive.
- Places the contents of file <string> at the top (as
comments) of all output RTL and simulation files.Tip: Use this option to ensure that the output RTL files contain user specified identification.
- Add top level event and stall ports required by kernel profiling.
- Specifies the top level function name as the prefix value.
This option is ignored if
config_rtl -module_prefixis also specified. This is enabled by default.
- Specifies a user-defined prefix to be added to all RTL entity/module names.
- Enable keep attribute.
- Register all I/O signals by default. The default is
false. This is enabled when the option is specified.
- Specifies the number of registers to add to the reset signal. In the Vivado IP flow the default is 0. For the Vitis kernel flow, the default value is 3.
-reset [none | control | state | all]
- Variables initialized in the C/C++ code are always
initialized to the same value in the RTL and therefore in the bitstream.
This initialization is performed only at power-on. It is not repeated when a
reset is applied to the design.
The setting applied with the
-resetoption determines how registers and memories are reset.
- No reset is added to the design.
- Resets control registers, such as those used in state machines and those used to generate I/O protocol signals. This is the default setting.
- Resets control registers and registers or memories derived from static or global variables in the C/C++ code. Any static or global variable initialized in the C/C++ code is reset to its initialized value.
- Resets all registers and memories in the design. Any static or global variable initialized in the C/C++ code is reset to its initialized value.
- Causes all registers to use a asynchronous reset. If this option is not specified, a synchronous reset is used.
-reset_level (low | high)
- Allows the polarity of the reset signal to be either
active-Low or active-High. The default is
Configures the output RTL to have all registers reset with an asynchronous active-Low reset.
config_rtl -reset all -reset_async -reset_level low
Adds the contents of
my_message.txt as a comment to all RTL output files.
config_rtl -header my_mesage.txt