cosim_design - 2021.2 English

Vitis High-Level Synthesis User Guide (UG1399)

Document ID
English (United States)
Release Date
2021.2 English


Executes post-synthesis co-simulation of the synthesized RTL with the original C/C++-based test bench.

Tip: To specify the files for the test bench run the following command:
add_files -tb

The simulation results are written to the sim/Verilog or sim/VHDL folder of the active solution, depending on the setting of the -rtl option.


cosim_design [OPTIONS]


Enables optimized compilation of the C/C++ test bench and RTL wrapper. This increases compilation time, but results in better runtime performance.
-argv <string>
The <string> is passed onto the main C/C++ function.

Specifies an argument list for the behavioral test bench.

-compiled_library_dir <string>
Specifies the compiled library directory during simulation with third-party simulators. The <string> is the path name to the compiled library directory. The library must be compiled ahead of time using the compile_simlib command as explained in the Vivado Design Suite Tcl Command Reference Guide (UG835).
Enables the coverage feature during simulation with the VCS simulator.
Disables the deadlock detection feature in co-simulation.
Disables dependency checks when running co-simulation.
This option turns on the dataflow channel profiling to track channel sizes during co-simulation.
This option turns on automatic FIFO channel size tuning for dataflow profiling during co-simulation.
-ldflags <string>
Specifies the options passed to the linker for co-simulation.

This option is typically used to pass include path information or library information for the C/C++ test bench.

-mflags <string>
Specifies options required for simulation.
Enable random stalling of top-level interfaces during co-simulation.
-rtl [verilog | vhdl]
Specifies which RTL language to use for C/RTL co-simulation. The default is Verilog.
Creates all simulation files created in the sim/<HDL> directory of the active solution. The simulation is not executed, but can be run later from a command shell.
Enable s_axilite to configure registers which are stable compared with the prior transaction.
-tool [auto | vcs | modelsim | riviera | isim | xsim | ncsim | xceilum]
Specifies the simulator to use to co-simulate the RTL with the C/C++ test bench. The Vivado simulator (xsim) is the default, unless otherwise specified.
-trace_level [*none* | all | port | port_hier]
Determines the level of waveform trace data to save during C/RTL co-simulation.
  • none does not save trace data. This is the default.
  • all results in all port and signal waveforms being saved to the trace file.
  • port only saves waveform traces for the top-level ports.
  • port_hier save the trace information for all ports in the design hierarchy.

The trace file is saved in the sim/Verilog or sim/VHDL folder of the current solution when the simulation executes, depending on the selection used with the -rtl option.

-user_stall <string>
Specifies the JSON stall file to be used during co-simulation. The stall file can be generated using the cosim_stall command.
Opens the Vivado simulator GUI to view waveforms and simulation results. Enables waveform viewing of all processes in the generated RTL, as in the dataflow and sequential processes. This option is only supported when using Vivado simulator for co-simulation by setting -tool xsim. See Viewing Simulation Waveforms for more information.


Performs verification using the Vivado simulator:


Uses the VCS simulator to verify the Verilog RTL and enable saving of the waveform trace file:

cosim_design -tool VCS -rtl verilog -coverage -trace_level all

Verifies the VHDL RTL using ModelSim. Values 5 and 1 are passed to the test bench function and used in the RTL verification:

cosim_design -tool modelsim -rtl vhdl -argv "5 1"