Executes post-synthesis co-simulation of the synthesized RTL with the original C/C++-based test bench.
The simulation results are written to the sim/Verilog or sim/VHDL folder
of the active solution, depending on the setting of the
- Enables optimized compilation of the C/C++ test bench and RTL wrapper. This increases compilation time, but results in better runtime performance.
<string>is passed onto the main C/C++ function.
Specifies an argument list for the behavioral test bench.
- Specifies the compiled library directory during simulation
with third-party simulators. The
<string>is the path name to the compiled library directory. The library must be compiled ahead of time using the
compile_simlibcommand as explained in the Vivado Design Suite Tcl Command Reference Guide (UG835).
- Enables the coverage feature during simulation with the VCS simulator.
- Use plain text test vector files instead of compressed binary format.
- Disables the deadlock detection feature in co-simulation.
- Disables dependency checks when running co-simulation.
- This option turns on the dataflow channel profiling to track channel sizes during co-simulation.
- This option turns on automatic FIFO channel size tuning for dataflow profiling during co-simulation.
- This option enables simulation of
ap_ctrl_nonewith stable top pointers.
- Specifies the location of test vectors generated during
hardware emulation to be used during co-simulation. The test vectors are
generated by the
config_export -cosim_trace_generationcommand. The argument lets you specify the kernel and instance name of the Vitis kernel in the hardware emulation simulation results to locate the test vectors.
- Specifies the options passed to the linker for
This option is typically used to pass include path information or library information for the C/C++ test bench.
- Specifies options required for simulation.
- Enable random stalling of top-level interfaces during co-simulation.
-rtl [verilog | vhdl]
- Specifies which RTL language to use for C/RTL co-simulation. The default is Verilog.
- Creates all simulation files created in the sim/<HDL> directory of the active solution. The simulation is not executed, but can be run later from a command shell.
s_axiliteto configure registers which are stable compared with the prior transaction.
-trace_level [*none* | all | port | port_hier]
- Determines the level of waveform trace data to save during
nonedoes not save trace data. This is the default.
allresults in all port and signal waveforms being saved to the trace file.
portonly saves waveform traces for the top-level ports.
port_hiersave the trace information for all ports in the design hierarchy.
The trace file is saved in the sim/Verilog or sim/VHDL folder of the current solution when the simulation executes, depending on the selection used with the
- Specifies the JSON stall file to be used during
co-simulation. The stall file can be generated using the
- Opens the Vivado
simulator GUI to view waveforms and simulation results. Enables waveform
viewing of all processes in the generated RTL, as in the dataflow and
sequential processes. This option is only supported when using Vivado simulator for co-simulation by
-tool xsim. See Viewing Simulation Waveforms for more information.
Performs verification using the Vivado simulator:
Uses the VCS simulator to verify the Verilog RTL and enable saving of the waveform trace file:
cosim_design -tool VCS -rtl verilog -coverage -trace_level all
Verifies the VHDL RTL using ModelSim. Values 5 and 1 are passed to the test bench function and used in the RTL verification:
cosim_design -tool modelsim -rtl vhdl -argv "5 1"