set_directive_loop_flatten - 2021.2 English

Vitis High-Level Synthesis User Guide (UG1399)

Document ID
UG1399
ft:locale
English (United States)
Release Date
2021-12-15
Version
2021.2 English

Description

Flattens nested loops into a single loop hierarchy.

In the RTL implementation, it costs a clock cycle to move between loops in the loop hierarchy. Flattening nested loops allows them to be optimized as a single loop. This saves clock cycles, potentially allowing for greater optimization of the loop body logic.

  • Perfect loop nests
    • Only the innermost loop has loop body content.
    • There is no logic specified between the loop statements.
    • All loop bounds are constant.
  • Semi-perfect loop nests
    • Only the innermost loop has loop body content.
    • There is no logic specified between the loop statements.
    • The outermost loop bound can be a variable.
  • Imperfect loop nests

    When the inner loop has variables bounds (or the loop body is not exclusively inside the inner loop), try to restructure the code, or unroll the loops in the loop body to create a perfect loop nest.

Syntax

set_directive_loop_flatten [OPTIONS] <location>
  • <location> is the location (inner-most loop), in the format function[/label].

Options

-off
Option to prevent loop flattening from taking place, and can prevent some loops from being flattened while all others in the specified location are flattened.
Important: The presence of the LOOP_FLATTEN pragma or directive enables the optimization. The addition of -off disables it.

Examples

Flattens loop_1 in function foo and all (perfect or semi-perfect) loops above it in the loop hierarchy, into a single loop. Place the pragma in the body of loop_1.

set_directive_loop_flatten foo/loop_1
#pragma HLS loop_flatten

Prevents loop flattening in loop_2 of function foo. Place the pragma in the body of loop_2.

set_directive_loop_flatten -off foo/loop_2
#pragma HLS loop_flatten off