This commands specifies a region of code, a protocol region, in which no clock operations will be inserted by Vitis HLS unless explicitly specified in the code. The tool will not insert any clocks between operations in the region, including those which read from or write to function arguments. The order of read and writes will therefore be strictly followed in the synthesized RTL.
lines of code
A clock operation can be explicitly specified in C code using an
ap_wait() statement, and can be specified in C++ code
by using the
wait statements have no effect on the
simulation of the design.
<location> specifies the location
(in the format
function[/label]) at which the
protocol region is defined.
mode=[floating | fixed]
floating: Lets code statements outside the protocol region overlap and execute in parallel with statements in the protocol region in the final RTL. The protocol region remains cycle accurate, but outside operations can occur at the same time. This is the default mode.
fixed: The fixed mode ensures that statements outside the protocol region do not execute in parallel with the protocol region.
io_section in function
following directive defines that region as a fixed mode protocol