Configure FSBL Parameters - 2021.2 English

Vitis Unified Software Platform Documentation: Embedded Software Development (UG1400)

Document ID
UG1400
ft:locale
English (United States)
Release Date
2021-12-15
Version
2021.2 English

Changing the first stage bootloader (FSBL) configuration is only available for the fixed design flow of the System Performance Modeling application.

To invoke the FSBL Configuration Change page, right-click the configuration name and select Configure FSBL Parameters.

Below are the details about the first stage bootloader (FSBL) parameters.

Table 1. FSBL Parameters

Parameter

Description

Default Value

PS Clock Frequency (MHz)

The clock frequency of the Zynq-7000 SoC PS (specified in MHz).

666.7 MHz

PL Clock Frequency (MHz)

The clock frequency of the Zynq-7000 SoC PL (specified in MHz).

100.0 MHz

DDR Clock Frequency (MHz)

The clock frequency of the DDR memory (specified in MHz).

533.3 MHz

DDR Data Path Width

The bit width used in the DDR memory data path. Possible values are 16 and 32 bits.

32 bits

DDR Port 0 - Enable HPR

This enables the usage of high priority reads on DDR port 0. This port is used by the CPUs and the ACP via the L2 Cache.

Unchecked

DDR Port 1 - Enable HPR

This enable the usage of high priority reads on DDR port 1. This port is used by other masters via the central interconnect.

Unchecked

DDR Port 2 - Enable HPR

This enables the usage of high priority reads on DDR port 2. This port is used by HP2 and HP3.

Unchecked

DDR Port 3 - Enable HPR

This enable the usage of high priority reads on DDR port 3. This port is used by HP0 and HP1.

Unchecked

HPR/LPR Queue Partitioning

Indicates the desired partitioning for high and low priority reads in the queue. Note that the queue has a depth of 32 read requests. There are four values provided in a drop-down menu.

HPR(0)/LPR(32)

LPR to Critical Priority Level

The number of clocks that the LPR queue can be starved before it goes critical. Unit: 32 DDR clock cycles. This value sets the DDR LPR_reg register [1]. Valid values are between 0 and 2047.

2

HPR to Critical Priority Level

The number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 DDR clock cycles. This value sets the DDR HPR_reg register [1]. Valid values are between 0 and 2047.

15

Write to Critical Priority Level

The number of clocks that the write queue can be starved before it goes critical. Unit: 32 DDR clock cycles. This value sets the DDR WR_reg register [1]. Valid values are between 0 and 2047.

2

For more information about the FSBL, refer to Zynq-7000 SoC Software Developers Guide (UG821).