Xilinx hardware designs are created with the Vivado® Design Suite, and can be exported in the Xilinx Support Archive (XSA) proprietary file format that can be then used by the Vitis software platform. For information on how to create an embedded design in Vivado and generate the XSA file, see the following embedded design tutorials:
- Zynq-7000 SoC: Embedded Design Tutorial (UG1165)
- Zynq UltraScale+ MPSoC: Embedded Design Tutorial (UG1209)
- Xilinx Embedded Design Tutorials: Versal Adaptive Compute Acceleration Platform (UG1305)
The generic steps are as follows:
- Create a Vivado project.
- Create a block design.
- Generate the image or bitstream.
- Export the hardware using Fixed Platform option. , and then select the