MicroBlaze Assembler - 2021.2 English

Vitis Unified Software Platform Documentation: Embedded Software Development (UG1400)

Document ID
UG1400
ft:locale
English (United States)
Release Date
2021-12-15
Version
2021.2 English

The mb-as assembler for the MicroBlaze soft processor supports the same set of options supported by the standard GNU compiler tools. It also supports the same set of assembler directives supported by the standard GNU assembler.

The mb-as assembler supports all the opcodes in the MicroBlaze machine instruction set, with the exception of the imm instruction. The mb-as assembler generates imm instructions when large immediate values are used. The assembly language programmer is never required to write code with imm instructions. For more information on the MicroBlaze instruction set, refer to the MicroBlaze Processor Reference Guide (UG081).

The mb-as assembler requires all MicroBlaze instructions with an immediate operand to be specified as a constant or a label. If the instruction requires a PC-relative operand, then the mb-as assembler computes it and includes an imm instruction if necessary.

For example, the branch immediate if equal (beqi) instruction requires a PC-relative operand.

The assembly programmer should use this instruction as follows:

beqi r3, mytargetlabel

where mytargetlabel is the label of the target instruction. The mb-as assembler computes the immediate value of the instruction as mytargetlabel - PC.

If this immediate value is greater than 16 bits, the mb-as assembler automatically inserts an imm instruction. If the value of mytargetlabel is not known at the time of compilation, the mb-as assembler always inserts an imm instruction. Use the relax option of the linker remove any unnecessary imm instructions.

Similarly, if an instruction needs a large constant as an operand, the assembly language programmer should use the operand as is, without using an imm instruction. For example, the following code adds the constant 200,000 to the contents of register r3, and stores the results in register r4:

addi r4, r3, 200000

The mb-as assembler recognizes that this operand needs an imm instruction, and inserts one automatically.

In addition to the standard MicroBlaze instruction set, the mb-as assembler also supports some pseudo-op codes to ease the task of assembly programming. The following table lists the supported pseudo-opcodes.

Table 1. Pseudo-Opcodes Supported by the GNU Assembler
Pseudo Opcodes Explanation
nop No operation. Replaced by instruction: or R0, R0, R0
la Rd, Ra, Imm Replaced by instruction: addik Rd, Ra, imm; = Rd = Ra + Imm;
not Rd, Ra Replace by instruction: xori Rd, Ra, -1
neg Rd, Ra Replace by instruction: rsub Rd, Ra, R0
sub Rd, Ra, Rb Replace by instruction: rsub Rd, Rb, Ra