When a processor is selected as an active target, any memory read/write commands (mrd/mwr) run by the users are executed by the processor. The debugger injects load/store instructions into the processor to access the memory. Because the processor executes these instructions, MMU and caches come into the picture. The address of the read/write commands is treated as virtual address by the processor. Data is read from or written to caches. If MMU and caches are disabled, physical memory is accessed during load/store.
Example, processor targets are Cortex-A9, Cortex®-A53, Cortex-A72, and so on.