Zynq UltraScale+ MPSoC Boot Header Attribute Bits - 2021.2 English

Vitis Unified Software Platform Documentation: Embedded Software Development (UG1400)

Document ID
UG1400
ft:locale
English (United States)
Release Date
2021-12-15
Version
2021.2 English
Table 1. Zynq UltraScale+ MPSoC Boot Header Attribute Bits
Field Name Bit Offset Width Default Description
Reserved 31:16 16 0x0 Reserved. Must be 0.
BHDR RSA 15:14 2 0x0
  • 0x3: RSA Authentication of the boot image will be done, excluding verification of PPK hash and SPK ID.
  • All Others others : RSA Authentication will be decided based on eFuse RSA bits.
Reserved 13:12 2 0x0 NA
CPU Select 11:10 2 0x0
  • 0x0: R5 Single
  • 0x1: A53 Single 32-bit
  • 0x2: A53 Single 64-bit
  • 0x3: R5 Dual
Hashing Select 9:8 2 0x0
  • 0x0, 0x1 : No Integrity check
  • 0x3: SHA3 for BI integrity check
PUF-HD 7:6 2 0x0
  • 0x3: PUF HD is part of boot header.
  • All other: PUF HD is in eFuse
Reserved 5:0 6 0x0 Reserved for future use. Must be 0.