Zynq UltraScale+ MPSoC Partition Attribute Bits - 2021.2 English

Vitis Unified Software Platform Documentation: Embedded Software Development (UG1400)

Document ID
UG1400
ft:locale
English (United States)
Release Date
2021-12-15
Version
2021.2 English

The following table describes the Partition Attribute bits on the partition header table for the Zynq® UltraScale+™ MPSoC.

Table 1. Zynq® UltraScale+™ MPSoC Device Partition Attribute Bits
Bit Offset Field Name Description
31:24 Reserved  
23 Vector Location Location of exception vector.
  • 0: LOVEC (default)
  • 1: HIVEC
22:20 Reserved  
19 Early Handoff
Handoff immediately after loading:
  • 0: No Early Handoff
  • 1: Early Handoff Enabled
18 Endianness
  • 0: Little Endian
  • 1: Big Endian
17:16 Partition Owner
  • 0: FSBL
  • 1: U-Boot
  • 2 and 3: Reserved
15 RSA Authentication Certificate present
  • 0: No RSA Authentication Certificate
  • 1: RSA Authentication Certificate
14:12 Checksum Type
  • 0: None
  • 1-2: Reserved
  • 3: SHA3
  • 4-7: Reserved
11:8 Destination CPU
  • 0: None
  • 1: A53-0
  • 2: A53-1
  • 3: A53-2
  • 4: A53-3
  • 5: R5-0
  • 6: R5 -1
  • 7 R5-lockstep
  • 8: PMU
  • 9-15: Reserved
7 Encryption Present
  • 0: Not Encrypted
  • 1: Encrypted
6:4 Destination Device
  • 0: None
  • 1: PS
  • 2: PL
  • 3-15: Reserved
3 A5X Exec State
  • 0: AARCH64 (default)
  • 1: AARCH32
2:1 Exception Level
  • 0: EL0
  • 1: EL1
  • 2: EL2
  • 3: EL3
0 Trustzone
  • 0: Non-secure
  • 1: Secure