Zynq UltraScale+ MPSoC Register Initialization Table - 2021.2 English

Vitis Unified Software Platform Documentation: Embedded Software Development (UG1400)

Document ID
UG1400
ft:locale
English (United States)
Release Date
2021-12-15
Version
2021.2 English

The Register Initialization Table in Bootgen is a structure of 256 address-value pairs used to initialize PS registers for MIO multiplexer and flash clocks. For more information, see Initialization Pairs and INT File Attribute.

Table 1. Zynq UltraScale+ MPSoC Register Initialization Table
Address Offset Parameter Description
0xB8 to 0x8B4 Register Initialization Pairs: <address>:<value>:

(2048 bytes)

If the Address is set to 0xFFFFFFFF, that register is skipped and the value is ignored. All unused register fields must be set to Address=0xFFFFFFFF and value =0x0.