exception_level - 2021.2 English

Vitis Unified Software Platform Documentation: Embedded Software Development (UG1400)

Document ID
UG1400
ft:locale
English (United States)
Release Date
2021-12-15
Version
2021.2 English

Syntax

  • For Zynq devices and Zynq UltraScale+ MPSoC:
    [exception_level=<options>] <partition>
  • For Versal® ACAP:
    { exception_level=<options>, file=<partition> }

Description

Exception level for which the core should be configured.

Arguments

  • el-0
  • el-1
  • el-2
  • el-3 (default)

Example

  • For Zynq devices and Zynq UltraScale+ MPSoC:
    all:
    {
    	[bootloader, destination_cpu=a53-0]fsbl.elf
    	[destination_cpu=a53-0, exception_level=el-3] bl31.elf
    	[destination_cpu=a53-0, exception_level=el-2] u-boot.elf
    }
  • For Versal® ACAP:
    new_bif:
    {
    	image
    	{
    		{ type = bootimage, file = base.pdi }
    	}
    	image
    	{
    		name = apu_ss, id = 0x1c000000
    		{ load = 0x1000, file = system.dtb }
                            { exception_level = el-2, file = u-boot.elf }
                            { core = a72-0, exception_level = el-3, trustzone, file = bl31.elf }
    	}
    }
    
Note: *base.pdi is the PDI generated by Vivado.