init - 2021.2 English

Vitis Unified Software Platform Documentation: Embedded Software Development (UG1400)

Document ID
UG1400
ft:locale
English (United States)
Release Date
2021-12-15
Version
2021.2 English

Syntax

  • For Zynq devices and Zynq UltraScale+ MPSoC:
    [init] <filename>
  • For Versal® ACAP:
    init = <filename>

Description

Register initialization block at the end of the bootloader, built by parsing the .int file specification. Maximum of 256 address-value init pairs are allowed. The .int files have a specific format.

Example

A sample BIF file is shown below:

  • For Zynq devices and Zynq UltraScale+ MPSoC:
    all:                                                     
     {                                                        
        [init] test.int                                       
     }
  • For Versal® ACAP:
    all:                                                     
     {                                                        
        init = reginit.int                                    
        image                                                 
        {                                                     
          name = image1, id = 0x1c000001                      
          { type=bootloader, file=plm.elf }                   
          { type=pmcdata, file=pmc_cdo.bin }                  
        }                                                     
     }