[Figure 1, callout 20 and 21]
The VMK180 evaluation board supports the VITA 57.4 FPGA mezzanine card (FMC+ or FMCP) specification by providing a subset implementation of the high pin count connectors at J51 (FMCP1) and J53 (FMCP2). FMC+ connectors use a 14 x 40 form factor, populated with 560 pins. The connector is keyed so that a mezzanine card, when installed on the VMK180 evaluation board, faces away from the board.
The FMCP1 DP[0:11] are connected across the Versal device U1 GTY201-GTY203. The FMCP2 DP[0:11] are connected across the Versal device U1 GTY204-GTY206. The FMCP1 and FMCP2 LA[0:33] bus and differential CLK pairs are connected across the banks 706, 707, and 708 triplet.
The detailed Versal adaptive SoC connections for the feature described in this section are documented in the VMK180 board XDC file, referenced in Xilinx Design Constraints.