GTY103/104: PCI Express Card Edge Connectivity

VMK180 Evaluation Board User Guide (UG1411)

Document ID
UG1411
Release Date
2023-06-09
Revision
1.2 English

[Figure 1, callout 15]

The 8-lane PCI Express card edge connector P3 supports operation up to Gen4 x8. P3 supports data transfers at the rate of 2.5 GT/s for Gen1 applications, 5.0 GT/s for Gen2 applications, 8.0 GT/s for Gen3 applications, and 16.0 GT/s for Gen4 applications. The PCIe transmit and receive signal data paths have a characteristic impedance of 85Ω ±10%. The PCIe_EP_REFCLK_P/N PCIe reference clock (routed as a 100Ω differential pair) received from J18 is routed to IDT 85411AMLF U39 1:2 buffer, which retransmits the clock as PCIe_CLK0 and PCIe_CLK1. U39 output Q0 PCIe_CLK0_P/N is routed to GTY103 (PCIe_EP_TX/RX[3:0]_P/N) and output Q1 PCIe_CLK1_P/N is routed to GTY104 (PCIe_TX/RX[7:4]_P/N).

For additional information about the Versal adaptive SoC PCIe functionality, see the Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343). Additional information about the PCI Express standard is available at the PCI-SIG website.

The detailed Versal adaptive SoC connections for the feature described in this section are documented in the VMK180 board XDC file, referenced in Xilinx Design Constraints.