HDMI Video Output (TX)

VMK180 Evaluation Board User Guide (UG1411)

Document ID
UG1411
Release Date
2023-06-09
Revision
1.2 English

[Figure 1, callout 18 and 19]

The VMK180 board provides an HDMI™ video output using a TI SN65DP159RGZ HDMI retimer at U43. The HDMI output is provided on a TE Connectivity 1888811-1 right-angle dual-stacked HDMI type A receptacle at P2 (upper port). The SN65DP159RGZ device is a dual mode DisplayPort to transition-minimized differential signal (TMDS) retimer supporting digital video interface (DVI) 1.0 and HDMI 1.4b and 2.0 output signals. The SN65DP159RGZ device supports the dual mode standard version 1.1 type 1 and type 2 through the DDC link or AUX channel. The SN65DP159RGZ device supports data rates up to 6 Gb/s per data lane to support Ultra HD (4K x 2K/60 Hz) 8-bits per color high-resolution video and HDTV with 16-bit color depth at 1080p (1920 x 1080/60 Hz). The SN65DP159RGZ device can automatically configure itself as a re-driver at data rates <1 Gb/s, or as a retimer at more than this data rate. This feature can be turned off through I2C programming. The HDMI video transmit/receive block diagram is shown in the following figure.

The Versal adaptive SoC U1 bank 406 user logic can implement a clock recovery circuit and output the series resistor coupled HDMI_REC_CLK_OUT (pin L19) for jitter attenuation. The jitter attenuated U62 Q2 HDMI_8T49N241_OUT_P/N series capacitor coupled output clock is connected to the HDMI_TX/RX[0:3] interface GTY106 GTY_REFCLK1 pins E39 (P) and E40 (N).

Figure 1. HDMI Interface Block Diagram

The VMK180 board accepts HDMI video input on the TE Connectivity 1888811-1 right-angle dual-stacked HDMI type-A receptacle P2 (lower port). The HDMI TMDS signals are input to TI TMDS181 retimer U55, which then drives the series capacitor coupled HDMI RX signals to U1 XCVM1802 GTY bank 106. The VMK180 HDMI RX interface supports up to 4K 60 Hz resolutions. See the HDMI IP documentation for more details about resolutions, color spaces, and optional HDCP features supported by the U1 Versal adaptive SoC.

The HDMI clock recovery is detailed in PCIe Clock.

For AMD HDMI IP details, see the HDMI 1.4/2.0 Transmitter Subsystem Product Guide (PG235) and the HDMI Transmitter and Receiver Subsystem Answer Record 70514.

See the HDMI Transmitter and Receiver Subsystem Answer Record 70514 for HDMI-compliant references.

For more details on the TI SN65DP159RGZ and TMDS181 HDMI retimers, see the component data sheets on the Texas Instruments website. For more details on the IDT 8T49N241, see the component data sheet on the Integrated Device Technology, Inc. website.

The detailed Versal adaptive SoC connections for the feature described in this section are documented in the VMK180 board XDC file, referenced in Xilinx Design Constraints.