The Xilinx design constraints (XDC) file template for the VMK180 board provides for designs targeting the VMK180 evaluation board. Net names in the constraints listed correlate with net names on the latest VMK180 evaluation board schematic. Identify the appropriate pins and replace the net names with net names in the user RTL. See the Vivado Design Suite User Guide: Using Constraints (UG903) for more information.
The HSPC FMCP connectors J51 and J53 are connected to the Versal adaptive SoC U1 banks powered by the variable voltage VADJ_FMC. Because different FMC cards implement different circuitry, the FMC bank I/O standards must be uniquely defined by each customer.
Important: See the VMK180 board documentation ("Board Files"
check box) for the XDC file.