[Figure 1, callout 41]
The VMK180 board includes an IDT 85411 (U39) 1:2 clock buffer for the PCIe clock fan out to the Versal adaptive SoC. The 100 MHz PCIe_CLK_P/N clock from the PCIe 8-lane edge connector (P3) drives the U39 clock input.
The U39's buffered outputs are used to create differential clock pairs to the Versal device U1 GTY103/GTY104 PCIe interface:
- U39's Q0 PCIe_CLK0_P/N are connected to PCIe_TX/RX[0:3] interface GTY103 GTY_REFCLK0 pins W39 (P) and W40 (N), which are A/C coupled
- U39's Q1 PCIe_CLK1_P/N are connected to PCIe_TX/RX[4:7] interface GTY104 GTY_REFCLK0 pins R39 (P) and R40 (N), which are A/C coupled
- 1:2 clock buffer
- Q0: 100 MHz LVDS
- Q1: 100 MHz LVDS