[Figure 1, callout 45]
The VMK180 board has an I2C programmable SI570 low-jitter 3.3V LVDS differential oscillator (U205) driving SI53340 (U206) 2-to-4 clock buffer input CLK0. The clock buffer generates four copies of the input clock. The SI53340 CLK1 second input is driven by 8A34001 (U219) output Q2. The SI53340 input clock select is controlled by 2-pin header J306 with default jumper off, selecting the CLK0 SI570 input. At power-up, SI570 (U205) defaults to an output frequency of 100.000 MHz. User applications or the System Controller can change the output frequency within the range of 10 MHz to 945 MHz through the I2C bus interface. Power cycling the VMK180 board reverts this user clock to the default frequency of 100.000 MHz.
- Programmable oscillator: Silicon Labs SI570BAB000299DG (10 MHz-945 MHz range, 100.000 MHz default)
- I2C address
0x5F - LVDS differential output, total stability: 61.5 ppm
The four SI53340 (U206) outputs are connected as follows:
- Outputs
- Q0: SI570_8A34001_MUX_BUF0_P/N capacitor coupled to GTY201 FMCP1_DP[0:3]_C2M/M2C interface GTY_REFCLK0 pins AB11 (P) and AB10 (N)
- Q1: SI570_8A34001_MUX_BUF1_P/N capacitor coupled to GTY204 FMCP2_DP[0:3]_C2M/M2C interface GTY_REFCLK0 pins G13 (P) and G12 (N)
- Q2: SI570_8A34001_MUX_BUF2_P/N capacitor coupled to GTY205 FMCP2_DP[4:7]_C2M/M2C interface GTY_REFCLK0 pins E13 (P) and E12 (N)
- Q3: SI570_8A34001_MUX_BUF3_P/N capacitor coupled to GTY206 FMCP2_DP[8:11]_C2M/M2C interface GTY_REFCLK0 pins C13 (P) and C12 (N)
The connection details for the Versal adaptive SoC U1 connected clocks described in this section are documented in the VMK180 board XDC file, referenced in Xilinx Design Constraints.
For more details on the Silicon Labs SI570, SI5332, and SI53340 devices, see the Silicon Labs website.
For more details on the IDT 85411AMLF, 8T49N241, and 8A34001 devices, see the Integrated Device Technology, Inc. website.
For Versal adaptive SoC clocking information, see the Versal Adaptive SoC Clocking Resources Architecture Manual (AM003).