You can integrate the DPU into custom Vitis platforms to run AI applications with the Vitis™ software platform. There are some pre-compiled platforms that can be downloaded from the Xilinx® Vitis Embedded Platform Downloads. If you want to create a custom platform, see Vitis Unified Software Platform Documentation (UG1416).
To facilitate the DPU integration, Xilinx provides the DPU TRD and XVDPU TRD in which you can configure the DPU with different parameters to meet the performance and resource utilization requirements. For more details, see DPUCZDX8G for Zynq UltraScale+ MPSoCs (PG338) and Vitis DPU TRD flow. For DPUCVDX8G, see DPUCVDX8G for Versal ACAPs Product Guide (PG389) and the Vitis DPUCVDX8G TRD flow.
On the hardware side, the Vitis software platform integrates
the DPU as an RTL kernel. It requires two clocks:
clk2x. One interrupt is needed. The DPU may also
need multiple AXI HP interfaces.
On the software side, the platform needs to provide the XRT and ZOCL packages. The host application can use the XRT OpenCL™ API to control the kernel. The Vitis AI Runtime can control the DPU with XRT. ZOCL is the kernel module that talks to acceleration kernels. It needs a device tree node which has to be added.
For more details, see the Vitis AI Platform Creation tutorials.
If you use the Vivado® Design Suite for DPU integration, see the DPU TRD Vivado flow.
If you want to integrate the DPU into Alveo™ Data Center accelerator cards and other non-embedded platforms, contact email@example.com.