Xilinx is continuously improving the DPU IP and the compiler to support more operators with better performance. The following table lists some typical operations and the configurations such as kernel size, stride, etc. that the DPU can support. If the operation configurations exceed these limitations, the operator will be assigned to the CPU. Additionally, the operators that the DPU can support are dependent on the DPU types, ISA versions, and configurations.
You can configure the DPUs to suit your requirements. You can choose engines, adjust intrinsic parameters, and create your own DPU IP with TRD projects but this means that the limitations can be very different between configurations. Either use the following product guides for information on configuration or compile the model with your own DPU configuration. The compiler tells you which operators can be assigned to the CPU. The table shows a specific configuration of each DPU architecture.
- DPUCZDX8G for Zynq UltraScale+ MPSoCs Product Guide(PG338)
DPUCAHX8H for Convolutional Neural Networks Product Guide (PG367)
- DPUCVDX8G for Versal ACAPs Product Guide (PG389)
- DPUCVDX8H for Convolutional Neural Networks v1.0 LogiCORE IP Product Guide (PG403)
The following operators are primitively defined in different deep learning frameworks. The compiler can automatically parse these operators, transform them into the XIR format, and distribute them to DPU or CPU. These operators are partially supported by the tools, and they are listed here for your reference. According to the limitations, you can use Inspecting the Float Model to automatically check operators in your models.