Vitis AI Compiler - 3.5 English

Vitis AI User Guide (UG1414)

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3.5 English

The AMD Vitis™ AI compiler (VAI_C) serves as a unified interface for a family of compilers to optimize neural-network computations for various Deep Learning Processing Units ( DPUs). Each compiler maps a network model to a highly optimized DPU instruction sequence.

The simplified description of the VAI_C framework is shown in the following figure. After parsing the topology of the optimized and quantized input model, VAI_C constructs an internal computation graph as an intermediate representation (IR), therefore, a corresponding control flow and a data flow representation. It then performs multiple optimizations, such as computation node fusion, for example, when the batch norm is fused into a presiding convolution, efficient instruction scheduling by exploiting inherent parallelism or exploiting data reuse.

Figure 1. Vitis AI Compiler Framework

The Vitis AI Compiler generates the compiled model based on the DPU microarchitecture. Vitis AI supports several DPUs for different platforms and applications.

Table 1. DPUs on Different Hardware Platforms
DPU Name Hardware platform
DPUCZDX8G AMD Zynq™ UltraScale+™ MPSoC
DPUCVDX8G AMD Versal™ adaptive SoC VCK190 evaluation board, Versal AI Core Series
DPUCVDX8H Versal adaptive SoC VCK5000 evaluation kit
DPUCV2DX8G Versal adaptive SoC VEK280 evaluation board, Versal AI Edge series, Versal adaptive SoC V70 evaluation kit, Alveo V70 Accelerator Card