The 2D filter accelerator compute unit AXI4_MASTER (AXI4 interfaces) ports are connected to NoC master units (NMUs) via SmartConnect to access DDR memory (in IPI, each NMU is modeled with an S_AXI port on NOC IP instances). The 2D filter function is translated to RTL using the Vivado HLS compiler. The data motion network used to transfer video buffers to or from memory and to program parameters (such as video dimensions and filter coefficients) is inferred automatically by the v++ compiler within the Vitis tool. There is always a 1-to-1 mapping between the compute unit AXI4 interfaces and NMUs. The implications of this are:
- Enables customer compute units to contain 1 or more AXI4_MASTER ports, with each AXI4_MASTER port connected to a single NMU.
- Each NMU can provide up to ~15 Gbytes/second of bandwidth, so compute units with higher bandwidth requirements must have multiple AXI4_MASTER ports to connect to multiple NMUs.