| CIPS Component | Clock Frequency |
|---|---|
| ACPU | 1350 MHz |
| NOC | 1000 MHz |
| NPI | 300 MHz |
| Clock | Clock Source | Clock Frequency | Function |
|---|---|---|---|
| PL0 Clock | CIPS | 100 MHz | Clock source for clocking wizard |
| Clk_out1 | Clocking wizard | 150 MHz | Memory mapped AXI clock, accelerator clock |
| Clk_100MHz | Clocking wizard | 105 MHz | AXI4-Lite clock |
| Clk_200MHz | Clocking wizard | 200 MHz | MIPI D-PHY core clock, AXI4-Stream clock |
| Sys_clk0 | SI570 (external) | Variable | DDR clock |
| HDMI DRU clock | SI570 (external) | Variable | Clock for data recovery unit for low line rates |
The PL0 clock is provided by the PPLL inside the PMC domain and is used as the reference input clock for the clocking wizard instance inside the PL. This clock does not drive any loads directly. A clocking wizard instance is used to deskew the clock and to provide three phase-aligned output clocks, Clk_out1, Clk_100MHz, and Clk_200MHz.
The Clk_100MHz clock is generated by the clocking wizard instance. It is used to drive most of the AXI4-Lite control interfaces in the PL. AXI4-Lite interfaces are typically used in the control path to configure IP registers and, consequently, can operate at a lower frequency than datapath interfaces.
The Clk_out1 clock is generated by the clocking wizard instance. It is used to drive the memory mapped AXI interfaces of the capture pipelines in the PL. These interfaces are in the datapath and, consequently, are needed to support the maximum performance of 2160p60, which roughly corresponds to a 150 MHz clock at 4 ppc. The HLS-based IP core interfaces and Vitis generated modules are based on Clk_out1 rather than Clk_100MHz (HLS IPs typically share a common input clock between control and data interfaces).
For details on the HDMI TX and HDMI GT clocking structure and requirements, see the respective sections in the HDMI 1.4/2.0 Transmitter Subsystem Product Guide (PG235) and the HDMI GT Controller LogiCORE IP Product Guide (PG334). For HDMI TX, an external clock chip is used to generate the GT reference clock depending on the display resolution. Various other HDMI related clocks are derived from the respective GT reference clocks or generated internally by the HDMI GT controller.