This chapter describes the Ethernet platform using multi-rate media access control (MRMAC) IP. The Ethernet packets are transferred between the MRMAC and the external NIC via GTY on the VMK180 board.
The MRMAC 1588 subsystem design is composed of MRMAC hard IP with 1588 ToD timers. The reference design can operate as four independent 10GE Ethernet ports.
In the transmit direction, the application running on the ARM Cortex A72 can generate the Ethernet traffic based on the data stored in DDR memory. This data is transferred to the MRMAC core via AXI MCDMA and FIFO via a streaming interface. The processed data is then transferred to the external NIC on a remote host via GTY on the VMK180 board. The NIC is connected to the VMK180 board using QSFP cables.
In the receive direction, the external NIC generates ethernet packets. The data is received at the GTY interface and is transferred to the MRMAC core. The MRMAC sends this data via the streaming interface to the S2MM port of AXI MCDMA. The AXI MCDMA writes this data onto memory.