Hardware Design Components - 2020.2 English

Versal ACAP VMK180 Targeted Reference Design (UG1432)

Document ID
UG1432
Release Date
2021-01-08
Version
2020.2 English

The following figure shows the high-level Ethernet plarform block diagram. The hardware design submodules are described in the following sections.

Figure 1. Ethernet Platform High-Level Hardware Block Diagram

Control Interface and Processor Subsystem (CIPS)

The CIPS present in Versal ACAP devices contains high performance ARM A72 processors. On-chip cache memory are included along with a suite of hardened communication peripherals. The required CIPS peripherals are:
  • JTAG/UART: for connection to Vivado lab tools (such as for bitstream download and debug), to the on-card satellite controller (SC), and to program GT clocks
  • I2C: for connection to board peripherals such as on-board fan and programmable clock sources

Network-On-Chip (NoC)

Versal ACAP devices are designed around an NoC interconnect, which provides high bandwidth communication between different areas of the device. In this Platform NoC is be used to:
  • Transmit the streaming ethernet data received by the AXI MCDMA to the memory
  • Transmit the ethernet data from the memory to the MRMAC via the AXI MCDMA streaming interface
  • Allows the Arm-A72 processor within the processor subsystem (PS) to connect to DDR memory

DDR Memory Controllers

The VM1802 device contains four hardened DDR memory controllers (MCs) that are accessed via the NoC. NoC configuration into the MCs can support individual access to each of the four MCs, or alternatively, can support MC interleaving in either pairs or as a group of four. This NoC interleaving ability makes interleaved MCs appear as a single block of memory.

Multi Rate Media Access Control (MRMAC)

The Xilinx® Versal™ ACAP integrated 100G multirate Ethernet MAC (MRMAC) is a high performance, low latency, adaptable Ethernet integrated hard IP. The block can be configured for up to four ports with independent MAC and PHY functions at the IEEE Standard MAC rates from 10GE to 100GE, and an overall maximum bandwidth of 100GE. The IP supports various FECs and the IEEE 1588 standard for a Precision Clock Synchronization Protocol for Networked Measurement and Control Systems hardware timestamping.

The MRMAC IP has AXI stream ports at the transmit and receive ends. The ethernet packets are transmitted/received via these AXI streaming ports. It has an AXI-Lite interface for accessing the control information and the statistics of the data transfer of the IP.

Quad Base Gigabit Transceiver Interface (GTY)

The AXI MCDMA provides high-bandwidth direct memory access between memory and AXI4-Stream target peripherals.This is a standard AXI multi channel direct memory access IP used in the PL. This facilitates the transfer of the Ethernet packets from and to the MRMAC for MAC processing.