The following summarizes the Versal ACAP’s key features:
- PS architecture
- Arm® Cortex-A72 processors (APU) in full-power domain (FPD)
- Arm Cortex-R5F processors (RPU) in low-power domain (LPD)
- PMC architecture
- ROM code unit (RCU) to run BootROM and access the boot device
- Platform processing unit (PPU) to run the platform loader and manager (PLM)
- Programmable logic (PL)
- Integrated functionality (AI engine, 100G multirate Ethernet MAC)
- Interconnect
- Network on a chip (NoC)
- AXI4 and AXI4-Stream
- Programming interfaces
- Advanced peripheral bus (APB)
- NoC programming interface (NPI)
- CCIX PCIe module (CPM) I/O interconnect with local L2-cache
- System-level interrupts, errors, events, and service requests
- I/O connectivity architecture (buffers and transceivers)
- Clock and reset architectures
Note: These are generic features
available in all
Versal™
ACAPs, however, the TRD
does not support AI engines.
Note: Refer to the
Versal
ACAP Technical Reference Manual (AM011) Section III,
Platform Boot, Control, and Status for details on boot and
configuration flow.