Module Features

The CLK104 provides the following features:

• On-module dedicated low noise LDO regulators supply 3.3V power to the GP PLL and RF PLLs.
• I2C serial interface
• TI USB2ANY interface (customized adapter/cable is required)
• LEDs indicate lock status of GP PLL and RF PLLs
• Programmable tracking on-module TCXO clock (10 MHz), or an external reference clock through SMA or a recovered clock from the PL bank
• Clock distribution PLL reference clock options
  • External reference clock
    • Single-ended clock through SMA connector
    • 3 dB attenuation
    • AC coupled
  • Free running on-module reference clock
    • 10.0 MHz TCXO
    • Manual mute option
  • Recovered clock
    • Differential clock through interface connector
    • Routed to RFSoC PL bank on evaluation board

• Clock distribution PLL output clock options
  • ADC RF PLL and DAC RF PLL differential reference clock signals (two pairs)
  • Two single-ended SYNC signals for the ADC RF PLL and DAC RF PLL
  • RFSoC ADC and DAC differential reference clock signals (two pairs)
  • SYSREF differential clock signal (one pair)
  • RFSoC differential clocks for PL banks (three pairs)
  • Single-ended external reference clock to SMA connector
• RF clock options
  • ADC RF clocks (two pairs)
    • Programmable to any frequency up to 10 GHz
    • Programmable output power level, typical > 4 dBm
    • Phase noise performance: -131 dBc/Hz at 1 MHz offset with 4 GHz carrier
  • DAC clock options (two pairs)
    • Programmable to any frequency up to 10 GHz
    • Programmable output power level, typical > 4 dBm
    • Phase noise performance: -124 dBc/Hz at 1 MHz offset with 10 GHz carrier