LMK04828B (U2) is a dual loop jitter cleaner and clock generator. The first stage PLL (PLL1) is driven by either an external reference clock, the on-module TCXO reference clock (10.0 MHz), or the recovered reference clock from the RFSoC. An external 160.00 MHz VCXO provides a frequency-accurate, low-phase noise reference clock for the second stage PLL (PLL2). PLL2 operates with a wide-loop bandwidth and generates the input references and SYNC signal for the ADC/DAC RF PLLs (U5 and U7), the PLL reference clocks, the SYSREF signal for the RFSoC ADC/DAC, the reference clocks for the RFSoC PL banks, and the output reference clock for multi-tile and multi-board synchronization.
U2 can be configured in dual-loop mode if synchronization is not required between the outputs and reference input. If it is configured in nested 0-delay mode, either DCLKout6 or DCLKout8 needs to be selected by the feedback multiplexer, as it establishes a fixed deterministic phase relationship of the phase of PLL1 input reference to the phase of outputs. DCLKoutX can be driven from either the internal VCO or the output divider. The internal PLL2 VCO frequency range is 2,370 to 2,630 MHz and 2,920 to 3,080 MHz. Each DCLKoutX has a single clock output divider (from 2 to 32). The output of this divider can also be directed to SDCLKoutY, where Y=X+1. SDCLKoutY can be driven from either output divider or a common SYSREF divider (from 8 to 8,191).
As a part of frequency planning, you need to select the proper input frequency for the LMX2594. If possible, use the integer mode as it is preferred to avoid fractional spurs. For example, for a 3.93216 GHz output, select the input frequency at 245.76 MHz. For an 8 GHz output, select the input frequency at 300.00 MHz. New configuration designs should be assessed on the spectrum analyzer before use.