The CLK104 RF clock add-on card mates with RFSoC evaluation boards using a low profile, 120-pin, high-speed SAMTEC LPA connector. The following figure shows the mezzanine module connector pin-out and the table that follows identifies the pins.
Figure 1. LPA Connector Pin-out
|Pin||Signal Name||Description||LMK04828 Pin|
|E2||DAC_REFCLK_P||DAC REFCLK, routed to RFSoC DAC on board||DCLKout6*|
|B2||ADC_REFCLK_P||ADC REFCLK, routed to RFSoC ADC on board||DCLKout12*|
|B8||AMS_SYSREF_P||AMS SYSREF, routed to RFSoC SYSREF on board||SDCLKout3*|
|B15||PL_CLK_P||PL CLK, routed to PL bank on board||DCLKout8*|
|B12||PL_SYSREF_P||PL_SYSREF, routed to PL bank on board||SDCLKout9*|
|B18||DDR_PLY_CAP_SYNC_P||DDR Playback/Capture Sync, routed to PL bank on board||SDCLKout7*|
|E15||SFP_REC_CLK_P||Recovered clock from RFSoC PL banks||CLKin0|
|E9||SYNC_IN||SYNC signal routed to PL bank on board||SYNC|
|E18||CLK104_SCL||I2C bus SCL||--|
|E19||CLK104_SDA||I2C bus SDA||--|
|B5||CLK_SPI_MUX_SEL0||PLL SPI MUX SEL0||--|
|B6||CLK_SPI_MUX_SEL1||PLL SPI MUX SEL0||--|
Note: The output frequency, power level, and enable/disable of each LMK04828B output are subject to change as determined by the configuration files.