This chapter describes the targeted reference design (TRD) hardware
architecture. The following figure shows a block diagram of the design components inside
the Versal ACAP on the VCK190 board. See VCK190 Evaluation Board User Guide (UG1366) for more
information.
Figure 1. Hardware Block Diagram
At a high level, the design comprises three pipelines:
- Capture/input pipeline
- USB capture pipeline (PS)
- Single or quad MIPI CSI-2 Rx capture pipeline (FMC + PL)
- HDMI RX video and audio capture pipeline
- Processing Pipeline
- 2D filter processing pipeline
- Display/Output Pipeline
- HDMI TX display pipeline
- HDMI RX audio pipeline
The block diagram comprises two parts: platforms and accelerators.
- Platforms
- This mainly consist of I/O interfaces and their data motion network.
This is the fixed part of the design. Platforms supported in this
reference design:
- Platform 1: Single sensor MIPI CSI-2 Rx (capture), USB-UVC (capture), HDMI Tx (display)
- Platform 2: Quad sensor MIPI CSI-2 Rx (capture), USB-UVC (capture), HDMI Tx (display)
- Platform 3: HDMI Rx (capture), USB-UVC (capture), HDMI Tx (display)
- This mainly consist of I/O interfaces and their data motion network.
This is the fixed part of the design. Platforms supported in this
reference design:
- Accelerators
- This is a block which performs different video processing functions.
This is the variable part of the design. Hardware accelerators supported
in this reference design:
- 2D convolution filter in the PL
- 2D convolution filter in the AIE
- This is a block which performs different video processing functions.
This is the variable part of the design. Hardware accelerators supported
in this reference design:
The accelerator and corresponding data/control interfaces (AXI-MM, AXI-Lite, interrupts) are generated by the Vitis tool and is integrated into the platform.