Burst Inference - 2023.2 English

Vitis HLS Messaging (UG1448)

Document ID

UG1448

Release Date

2023-10-18

Version

2023.2 English

Description

Burst inference is not supported for ports with a cache.

Explanation

Two kinds of bursts are supported by HLS:

Statically inferred bursts

This method is more efficient, because there is no resource overhead or performance penalty. These are inferred in one of the following methods:

Automatically, when the HLS tool can do so. These bursts have the characteristics specified by the interface pragma (for example, maximum read or write burst length)
Manually, when you use the hls::burst_maxi class

Dynamically generated bursts when the cache reads a line: This method is less efficient, because there is a resource cost and a penalty. The entire line must be read before the requested element is returned to the kernel; this is significant with large cache lines. Therefore, these bursts always have the length of a cache line.

The cache prevents the inference of static bursts, and generates burst dynamically upon each miss.

Example

In the following code snippet, burst inference is not supported for port in because there is a cache required for port in.

void dut(unsigned int *in,  // Read-Only Vector 1
         unsigned int *out, // Output Result
         int size           // Size in integer
) {
 
#pragma HLS INTERFACE m_axi port = in bundle = aximm depth = 1024
#pragma HLS INTERFACE m_axi port = out bundle = aximm depth = 1024
 
#pragma HLS cache port = in lines = 1 depth = 128 burst = off
  for (int i = 0; i < size; i++) {
#pragma HLS pipeline II = 1
    out[i] = in[i] + 1;
  }
}